Vlsi Software List

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VLSI Layout 3D v.1.0 VLSI Layout 3d is a 3d visualization software for VLSI designs created in LASI. This project is gearing up to go open-source! VLSI Library v.1.0 This project aims to create and distribute a full featured VLSI library under free licenses in order to contribute to the open hardware community and to the progress of peoples.
Is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided, including a RAM generator, a ROM generator and a data-path compiler.

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HDL simulators are software packages that compile and simulate expressions written in one of the hardware description languages.

November 1997. Retrieved 3 June 2019. ^. Shaktimaan all episodes list. Archived from on 31 October 2003.

History[edit]

HDL simulation software has come a long way since its early origin as a single proprietary product offered by one company. Today, simulators are available from many vendors at various prices, including free ones. For desktop/personal use, Aldec, Mentor, LogicSim, SynaptiCAD,TarangEDA and others offer tool-suites under US$5000 for the Windows 2000/XP platform. The suites bundle the simulator engine with a complete development environment: text editor, waveform viewer, and RTL-level browser. Additionally, limited-functionality editions of the Aldec and ModelSim simulator are downloadable free of charge, from their respective OEM partners (Microsemi, Altera, Lattice Semiconductor, Xilinx, etc.) For those desiring open-source software, there is Icarus Verilog, GHDL among others.

Beyond the desktop level, enterprise-level simulators offer faster simulation runtime, more robust support for mixed-language (VHDL and Verilog) simulation, and most importantly, are validated for timing-accurate (SDF-annotated) gate-level simulation. The last point is critical for the ASIC tapeout process, when a design database is released to manufacturing. (semiconductor foundries stipulate the usage of tools chosen from an approved list, in order for the customer's design to receive signoff status. Although the customer is not required to perform any signoff checking, the tremendous cost of a wafer order has generally ensured thorough design validation on the part of the customer.) The three major signoff-grade simulators include Cadence Incisive Enterprise Simulator, Mentor ModelSim/SE, and Synopsys VCS. Pricing is not openly published, but all three vendors charge $25,000-$100,000 USD per seat, 1-year time-based license.

FPGA vendors do not require expensive enterprise simulators for their design flow. In fact, most vendors include an OEM version of a third-party HDL simulator in their design suite. The bundled simulator is taken from an entry-level or low-capacity edition, and bundled with the FPGA vendor's device libraries. For designs targeting high-capacity FPGA, a standalone simulator is recommended, as the OEM-version may lack the capacity or speed to effectively handle large designs.

In many cases VS10XX can also load the application from external EEPROM when booting. We classify customization software into the following categories: Plugin: Increases basic functionality; runs along with system firmware. Patch: Fixes software bugs or unwanted features. Remember to check if a patch set exists for your VS10XX IC!

Below is a list of various HDL simulators.

Commercial simulators[edit]

List of HDL simulators in alphabetical order by name
Simulator name	Author/company	Languages	Description
Active-HDL/Riviera-PRO	Aldec	VHDL-1987,-1993,-2002,-2008,V1995,V2001,V2005,SV2009	A simulator with complete design environment aimed at FPGA-applications. Aldec licenses Active-HDL to FPGA-vendors, and the underlying engine can be found in the design-suites of those vendors. While ActiveHDL is a low-cost product, Aldec also offers a more expensive, higher-performance simulator called 'Riviera-PRO'. With advanced debugging capabilities, it is aimed at the verification of large FPGA and ASIC devices using formal verification methodologies such as assertion based verification.
Aeolus-DS	Huada Empyrean Software Co.,Ltd	V2001	Aeolus-DS is a part of Aeolus simulator which is designed to simulate mixed signal circuit. Aeolus-DS supports pure Verilog simulation.
CVC	Tachyon Design Automation	V2001, V2005	CVC is a Verilog HDL compiled simulator. CVC has the ability to simulate in either interpreted or compiled mode.
HiLo	Teradyne	Used in 1980s.
Incisive Enterprise Simulator ('big 3')	Cadence Design Systems	VHDL-1987,-1993,-2002,-2008, V2001, SV2005, SV2009, SV2012	Cadence initially acquired Gateway Design, thereby acquiring Verilog-XL. In response to competition from faster simulators, Cadence developed its own compiled-language simulator, NC-Verilog. The modern version of the NCsim family, called Incisive Enterprise Simulator, includes Verilog, VHDL, and SystemVerilog support. It also provides support for the e verification language, and a fast SystemC simulation kernel.
ISE Simulator	Xilinx	VHDL-93, V2001	Xilinx's simulator comes bundled with the ISE Design Suite. ISE Simulator (ISim) provides support for mixed-mode language simulation including, but not limited to, simulation of designs targeted for Xilinx's FPGAs and CPLDs.
Metrics Cloud Simulator	Metrics Technologies	SV2012	SystemVerilog simulator used on the Metrics cloud platform. Includes all the standard features of a modern SystemVerilog simulator including debug, APIs, language and testbench support.
ModelSim and Questa ('big 3')	Mentor Graphics	VHDL-1987,-1993,-2002,-2008, V2001, SV2005, SV2009, SV2012	The original Modeltech (VHDL) simulator was the first mixed-language simulator capable of simulating VHDL and Verilog design entities together. In 2003, ModelSim 5.8 was the first simulator to begin supporting features of the Accellera SystemVerilog 3.0 standard.^[1] In 2005 Mentor introduced Questa to provide high performance Verilog and SystemVerilog simulation and expand Verification capabilities to more advanced methodologies such as Assertion Based Verification and Functional Coverage. Today Questa is the leading high performance SystemVerilog and Mixed simulator supporting a full suite of methodologies including industry standard OVM and UVM. ModelSim is still the leading simulator for FPGA design.
MPSim	Axiom Design Automation	V2001, V2005, SV2005, SV2009	MPsim is a fast compiled simulator with full support for Verilog, SystemVerilog and SystemC. It includes Designer, integrated Verilog and SystemVerilog debugging environment and has built-in support for multi-cpu simulation.
PureSpeed	Frontline	V1995	The first Verilog simulator available on the Windows OS. The simulator had a cycle-based counterpart called 'CycleDrive'. FrontLine was sold to Avant! in 1998, which was later acquired by Synopsys in 2002. Synopsys discontinued Purespeed in favor of its well-established VCS simulator.
Quartus II Simulator (Qsim)	Altera	VHDL-1993, V2001, SV2005	Altera's simulator bundled with the Quartus II design software in release 11.1 and later. Supports Verilog, VHDL and AHDL.
SILOS	Silvaco	IEEE-1364-2001	As one of the low-cost interpreted Verilog simulators, Silos III, from SimuCad, enjoyed great popularity in the 1990s. With Silvaco's acquisition of SimuCad, Silos is part of the Silvaco EDA tool suite.
SIMILI VHDL	Symphony EDA	VHDL-1993	Another low-cost VHDL simulator with graphical user interface and integrated waveform viewer. Their web site was not updated for quite some time now. You can no longer purchase the software. The free version does work but you have to request a license via email.
SMASH	Dolphin Integration	V1995, V2001, VHDL-1993	SMASH is a mixed-signal, multi-language simulator for IC or PCB designs. It uses SPICE syntax for analog descriptions, Verilog-HDL and VHDL for digital, Verilog-A/AMS, VHDL-AMS and ABCD (a combination of SPICE and C) for analog behavioral, and C for DSP algorithms.
Speedsim	Cadence Design Systems	V1995	Cycle based simulator originally developed at DEC. The DEC developers spun off to form Quickturn Design Systems. Quickturn was later acquired by Cadence, who discontinued the product in 2005. Speedsim featured an innovative slotted bit-slice architecture that supported simulation of up to 32 tests in parallel.
Super-FinSim	Fintronic	V2001	This simulator is available on multi-platform, claiming IEEE 1364-2001 compliance.
TEGAS/Texsim	TEGAS/CALMA/GE	TDL (Tegas Design Language)	First described in 1972 paper, used in 1980s by ASIC vendors such as LSI Logic, GE.
VCS ('big 3')	Synopsys	VHDL-1987,-1993,-2002,-2008, V2001, SV2005, SV2009, SV2012	Originally developed by John Sanguinetti, Peter Eichenberger and Michael McNamara under the startup company Chronologic Simulation, which was acquired by ViewLogic Systems in 1994. ViewLogic was subsequently acquired by Synopsys in 1997. VCS has been in continuous active development, and pioneered compiled-code simulation, native testbench and SystemVerilog support, and unified compiler technologies. Today, VCS provides comprehensive support for all functional verification methodologies and languages (including VHDL, Verilog, SystemVerilog, Verilog AMS, SystemC, and C/C++), and advanced simulation technologies including native low power, x-propagation, unreachability analysis, and fine-grained parallelism.
Verilogger Extreme, Verilogger Pro	SynaptiCAD	V2001,V1995	Verilogger Pro is a low-cost interpreted simulator based on Elliot Mednick's VeriWell code base. Verilogger Extreme is a newer, compiled-code simulator that is Verilog-2001 compliant and much faster than Pro.
Verilog-XL	Cadence Design Systems	V1995	The original Verilog simulator, Gateway Design's Verilog-XL was the first (and only, for a time) Verilog simulator to be qualified for ASIC (validation) sign-off. After its acquisition by Cadence Design Systems, Verilog-XL changed very little over the years, retaining an interpreted language engine, and freezing language-support at Verilog-1995. Cadence recommends Incisive Enterprise Simulator for new design projects, as XL no longer receives active development. Nevertheless, XL continues to find use in companies with large codebases of legacy Verilog. Many early Verilog codebases will only simulate properly in Verilog-XL, due to variation in language implementation of other simulators.
Veritak	Sugawara Systems	V2001	It is low-cost and Windows-based only. It boasts a built-in waveform viewer and fast execution.
Vivado Simulator	Xilinx	VHDL-93, V2001	Xilinx's Vivado Simulator comes as part of the Vivado design suite. It is a compiled-language simulator that supports mixed language, TCL scripts, encrypted IP and enhanced verification. Vivado is targeted at Xilinx's larger FPGAs, and is slowly replacing ISE as their mainline tool chain. As of mid 2014, Vivado covered Xilinx's mid scale and large FPGAs, and ISE covered the mid scale and smaller FPGAs and all CPLDs.
Z01X	WinterLogic (acquired by Synopsys 2016)	V2001,SV2005	Developed as a fault simulator but can also be used as a logic simulator.

Some non-free commercial simulators (such as ModelSim) are available in student, or evaluation/demo editions. These editions generally have many features disabled, arbitrary limits on simulation design size, but are offered free of charge.

Free and open-source simulators[edit]

List of Verilog simulators in alphabetical order
Simulator name	License	Author/company	Supported languages	Description
GPL Cver	GPL	Pragmatic C Software	V1995, minimal V2001	This is a GPL open-source simulator. It is a pure simulator. This simulator is not fully IEEE 1364-2001 compliant. It does not support generate and constant functions.
Icarus Verilog	GPL2+	Stephen Williams	V1995, V2001, V2005, limited SV2005/SV2009	Also known as iverilog. Good support for Verilog 2005, including generate statements and constant functions.
LIFTING	A. Bosio, G. Di Natale (LIRMM)	V1995	LIFTING (LIRMM Fault Simulator) is an open-source simulator able to perform both logic and fault simulation for single/multiple stuck-at faults and single event upset (SEU) on digital circuits described in Verilog.
OSS CVC	Perl style artistic license	Tachyon Design Automation	V2001, V2005	CVC is a Verilog HDL compiled simulator. CVC has the ability to simulate in either interpreted or compiled mode. Source code is available under a Perl style artistic license.
TkGate	GPL2+	Jeffery P. Hansen	V1995	Event driven digital circuit editor and simulator with tcl/tk GUI based on Verilog. Includes Verilog simulator Verga.
Verilator	GPL3	Veripool	Synthesizable V1995, V2001, V2005, SV2005, SV2009, SV2012, SV2017	This is a very high speed open-source simulator that compiles synthesizable Verilog to multithreaded C++/SystemC.
Verilog Behavioral Simulator (VBS)	GPL	Lay H. Tho and Jimen Ching	V1995	Supports functions, tasks and module instantiation. Still lacks a lot of features, but this release has enough for a VLSI student to use and learn Verilog. Supports only behavioral constructs of Verilog and minimal simulation constructs such as 'initial' statements.
VeriWell	GPL2	Elliot Mednick	V1995	This simulator used to be commercial, but has recently become GPL open-source. Compliance with 1364 is not well documented. It is not fully compliant with IEEE 1364-1995.
ISOTEL Mixed Signal & Domain	GPL	ngspice and Yosys communities, and Isotel	V2005	Open-source mixed signal ngspice simulator in combination with verilog synthesis software called Yosys and Isotel extension for embedded C/C++ (or other) co-simulation.

List of VHDL simulators in alphabetical order
Simulator name	License	Author/company	Supported languages	Description
GHDL	GPL2+	Tristan Gingold	VHDL-1987, VHDL-1993, VHDL-2002, partial VHDL-2008	GHDL is a complete VHDL simulator, using the GCC technology.
Icarus Verilog	GPL2+	Maciej Sumiński Stephen Williams	VHDL preprocessor added that converts VHDL to Verilog
nvc	GPL3	Nick Gasson	VHDL-1993

Key[edit]

Tag	Description
V1995	IEEE 1364-1995 Verilog
V2001	IEEE 1364-2001 Verilog
V2005	IEEE 1364-2005 Verilog
SV2005	IEEE 1800-2005 SystemVerilog
SV2009	IEEE 1800-2009 SystemVerilog
SV2012	IEEE 1800-2012 SystemVerilog
SV2017	IEEE 1800-2017 SystemVerilog
VHDL-1987	IEEE 1076-1987 VHDL
VHDL-1993	IEEE 1076-1993 VHDL
VHDL-2002	IEEE 1076-2002 VHDL
VHDL-2008	IEEE 1076-2008 VHDL

References[edit]

^http://www.sutherland-hdl.com/papers/2004-Mentor-U2U-presentation_SystemVerilog_and_ModelSim.pdf

Retrieved from 'https://en.wikipedia.org/w/index.php?title=List_of_HDL_simulators&oldid=913206962'

(Redirected from Very-large-scale integration)

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining millions of MOS transistors onto a single chip. VLSI began in the 1970s when MOS integrated circuit chips were widely adopted, enabling complex semiconductor and telecommunication technologies to be developed. The microprocessor and memory chips are VLSI devices. Before the introduction of VLSI technology, most ICs had a limited set of functions they could perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all of these into one chip.

A VLSI integrated-circuit die

History[edit]

The history of the transistor dates to the 1920s when several inventors attempted devices that were intended to control current in solid-state diodes and convert them into triodes. Success came after World War II, when the use of silicon and germanium crystals as radar detectors led to improvements in fabrication and theory. Scientists who had worked on radar returned to solid-state device development. With the invention of the first transistor at Bell Labs in 1947, the field of electronics shifted from vacuum tubes to solid-state devices.

With the small transistor at their hands, electrical engineers of the 1950s saw the possibilities of constructing far more advanced circuits. However, as the complexity of circuits grew, problems arose.^[1] One problem was the size of the circuit. A complex circuit like a computer was dependent on speed. Open sans free font download. If the components were large, the wires interconnecting them must be long. The electric signals took time to go through the circuit, thus slowing the computer.^[1]

The invention of the integrated circuit by Jack Kilby and Robert Noyce solved this problem by making all the components and the chip out of the same block (monolith) of semiconductor material. The circuits could be made smaller, and the manufacturing process could be automated. This led to the idea of integrating all components on a single-crystal silicon wafer, which led to small-scale integration (SSI) in the early 1960s, and then medium-scale integration (MSI) in the late 1960s.

Further integration was made possible with the wide adoption of the MOS transistor, originally invented by Mohamed Atalla and Dawon Kahng at Bell Labs in 1959.^[2] Atalla first proposed the concept of the MOS integrated circuit chip in 1960, followed by Kahng in 1961, both noting that the MOS transistor's ease of fabrication made it useful for integrated circuits.^[3]^[4]General Microelectronics introduced the first commercial MOSintegrated circuit in 1964.^[5] In the early 1970s, MOS integrated circuit technology allowed the integration of more than 10,000 transistors in a single chip.^[6] This paved the way for large-scale integration (LSI) and then VLSI in the 1970s and 1980s, with tens of thousands of MOS transistors on a single chip (later hundreds of thousands, then millions, and now billions).

The first semiconductor chips held two transistors each. Subsequent advances added more transistors, and as a consequence, more individual functions or systems were integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on a single device. Now known retrospectively as small-scale integration (SSI), improvements in technique led to devices with hundreds of logic gates, known as medium-scale integration (MSI). Further improvements led to large-scale integration (LSI), i.e. systems with at least a thousand logic gates. Current technology has moved far past this mark and today's microprocessors have many millions of gates and billions of individual transistors.

At one time, there was an effort to name and calibrate various levels of large-scale integration above VLSI. Terms like ultra-large-scale integration (ULSI) were used. But the huge number of gates and transistors available on common devices has rendered such fine distinctions moot. Terms suggesting greater than VLSI levels of integration are no longer in widespread use.

In 2008, billion-transistor processors became commercially available. This became more commonplace as semiconductor fabrication advanced from the then-current generation of 65 nm processes. Current designs, unlike the earliest devices, use extensive design automation and automated logic synthesis to lay out the transistors, enabling higher levels of complexity in the resulting logic functionality. Certain high-performance logic blocks like the SRAM (static random-access memory) cell, are still designed by hand to ensure the highest efficiency.

Structured design[edit]

Structured VLSI design is a modular methodology originated by Carver Mead and Lynn Conway for saving microchip area by minimizing the interconnect fabrics area. This is obtained by repetitive arrangement of rectangular macro blocks which can be interconnected using wiring by abutment. An example is partitioning the layout of an adder into a row of equal bit slices cells. In complex designs this structuring may be achieved by hierarchical nesting.^[7]

Structured VLSI design had been popular in the early 1980s, but lost its popularity later because of the advent of placement and routing tools wasting a lot of area by routing, which is tolerated because of the progress of Moore's Law. When introducing the hardware description language KARL in the mid' 1970s, Reiner Hartenstein coined the term 'structured VLSI design' (originally as 'structured LSI design'), echoing Edsger Dijkstra's structured programming approach by procedure nesting to avoid chaotic spaghetti-structured program

Difficulties[edit]

As microprocessors become more complex due to technology scaling, microprocessor designers have encountered several challenges which force them to think beyond the design plane, and look ahead to post-silicon:

Process variation – As photolithography techniques get closer to the fundamental laws of optics, achieving high accuracy in doping concentrations and etched wires is becoming more difficult and prone to errors due to variation. Designers now must simulate across multiple fabrication process corners before a chip is certified ready for production, or use system-level techniques for dealing with effects of variation.^[8]
Stricter design rules – Due to lithography and etch issues with scaling, design rules for layout have become increasingly stringent. Designers must keep in mind an ever increasing list of rules when laying out custom circuits. The overhead for custom design is now reaching a tipping point, with many design houses opting to switch to electronic design automation (EDA) tools to automate their design process.
Timing/design closure – As clock frequencies tend to scale up, designers are finding it more difficult to distribute and maintain low clock skew between these high frequency clocks across the entire chip. This has led to a rising interest in multicore and multiprocessor architectures, since an overall speedup can be obtained even with lower clock frequency by using the computational power of all the cores.
First-pass success – As die sizes shrink (due to scaling), and wafer sizes go up (due to lower manufacturing costs), the number of dies per wafer increases, and the complexity of making suitable photomasks goes up rapidly. A mask set for a modern technology can cost several million dollars. This non-recurring expense deters the old iterative philosophy involving several 'spin-cycles' to find errors in silicon, and encourages first-pass silicon success. Several design philosophies have been developed to aid this new design flow, including design for manufacturing (DFM), design for test (DFT), and Design for X.